The Celeron is a discontinued series of IA-32 and x86-64 computer microprocessors targeted at low-cost personal computers, manufactured by Intel from 1998 to 2023.
The first Celeron-branded CPU was introduced on April 15, 1998, and was based on the Pentium II. Starting with the Prescott Celeron D and Conroe Celeron M, Celeron processors have supported both 32-bit and 64-bit x86 software. They typically include smaller CPU caches and fewer features, resulting in lower performance compared to Intel’s mainstream brands Pentium or Core. While some Celeron designs have achieved strong performance for their segment, the majority of the Celeron line has exhibited noticeably degraded performance. Intel’s higher-end brands command premium prices in part because they offer larger caches and advanced features that Celeron processors lack.
In September 2022, Intel announced that the Celeron brand, along with Pentium, were to be replaced with the new "Intel Processor" branding for low-end processors starting on January 1, 2023. The Celeron had two cores, but the N100 has four cores. The maximum operating clock is 3.40GHz, the TDP is 6W. The maximum RAM capacity is 16GB.
Background
As a product concept, the Celeron was introduced in response to Intel's loss of the low-end market, in particular to the Cyrix 6x86, the AMD K6, and the IDT Winchip. Intel's existing low-end product, the Pentium MMX, was no longer performance-competitive at 233 MHz. Although a faster Pentium MMX would have been a lower-risk strategy, the industry-standard Socket 7 platform hosted a market of competitor CPUs that could be drop-in replacements for the Pentium MMX. Instead, Intel pursued a budget part that was to be pin-compatible with their high-end Pentium II product, using the Pentium II's proprietary Slot 1 interface.
The Celeron also effectively killed off the nine-year-old i486 chip, which had been the low-end processor brand for entry-level desktops and laptops until 1998.
Intel hired marketing firm Lexicon Branding, which had originally come up with the name "Pentium", to devise a name for the new product as well. The San Jose Mercury News described Lexicon's reasoning behind the name they chose: "Celer is Latin for swift, as in the word 'accelerate', and 'on' as in 'turned on'. Celeron is seven letters and three syllables, like Pentium. The 'Cel' of Celeron rhymes with 'tel' of Intel."
Discontinuation The Celeron range was discontinued on January 1st, 2023 by Intel. In September 2022, Intel announced that the Celeron brand, along with Pentium, were to be replaced with the new "Intel Processor" branding for low-end processors. Intel stated at the time that after the brand change they "will continue to deliver the same products and benefits within segments.” +Intel Celeron processor family Based on Desktop Laptop EmbeddedCode-namedCoreDate releasedCode-namedCoreDate releasedCode-namedCoreDate releasedP6CovingtonMendocinoCoppermine-128Tualatin-256(250 nm)(250 nm)(180 nm)(130 nm)19981998–20002000–20012002MendocinoCoppermine-128Coppermine TTualatin-256(250 nm)(180 nm)(180 nm)(130 nm)19992000–200120012002–2003NetBurstWillamette-128Northwood-128(180 nm)(130 nm)20022002–2003Northwood-256(130 nm)2002–2003Pentium M (Celeron M)Banias-512Dothan-512Dothan-1024Yonah-512Yonah-1024Sossaman(130 nm)(90 nm)(90 nm)(65 nm)(65 nm)(65 nm)20042004–20072004–2005200720062006–2007NetBurst (Celeron D)Prescott-256Cedar Mill-512(90 nm)(65 nm)2004–20052006–2007Core (Single)Conroe-LConroe-CL(65 nm)(65 nm)2007–2008200?Core (Dual)AllendaleWolfdale-3M(65 nm)(45 nm)2008–20092009–2010Core (Celeron M/Celeron)Merom, Merom-LMerom-2MMerom-L (Ultra-Low-Voltage)(65 nm)(65 nm)(65 nm)2007–200820082007, 2009Core (Celeron Dual)Merom-2MPenryn-3M(65 nm)(45 nm)20082009–2010Nehalem/WestmereClarkdale(32 nm)2010Arrandale(32 nm)2010–2011Jasper ForestSingle (45 nm)SilvermontAirmontGoldmontGoldmont PlusTremontBay Trail-BraswellApollo LakeGemini LakeJasper Lakedual & quad (22 nm)dual & quad (14 nm)up to quad (14 nm)up to quad (14 nm)up to quad (10 nm)Bay Trail-MBraswellApollo LakeGemini LakeJasper Lakedual & quad (22 nm)dual & quad (14 nm)up to quad (14 nm)up to quad (14 nm)up to quad (10 nm)October 2013March 2015April 2016December 2017January 2021Bay Trail-MBraswellApollo LakeGemini LakeJasper Lakedual & quad (22 nm)dual & quad (14 nm)up to quad (14 nm)up to dual (14 nm)up to dual (10 nm)October 2013March 2015April 2016December 2017January 2021List of Intel Celeron processors
Desktop Celerons
P6-based Celerons
The first family of the Celerons are Intel's family of desktop IA-32 CPUs based on the sixth-generation P6 microarchitecture, which is the low-end variant of the Pentium II and later the Pentium III. The brand's initial processors were very similar to the earlier Pentium II-branded processors. Coppermine-based Celerons added support for the Streaming SIMD Extensions (SSE) instruction set (to accelerate floating point and parallel calculations), and the introduction of a controversial serial number embedded in the chip during manufacturing (absent on Tualatin and later Intel processors).
The final shipments of the original P6 Celerons for desktop units occurred on April 23, 2004.
Covington
Launched in April 1998, the first Covington Celeron was essentially a 266 MHz Pentium II manufactured without any secondary cache at all. Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300 MHz (frequencies 33 or 66 MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons had trouble outcompeting the parts they were designed to replace. Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals. The initial market interest faded rapidly in the face of its poor performance, and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless, the first Celerons were quite popular among some overclockers, for their flexible overclockability and reasonable price. Covington was only manufactured in Slot 1 SEPP format.
Mendocino
The Mendocino Celeron, launched August 24, 1998, was the first retail CPU to use on-die L2 cache. Whereas Covington had no secondary cache at all, Mendocino included 128 KB of L2 cache running at full clock rate. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron 300A. Although the other Mendocino Celerons (the 333 MHz part, for example) did not have an A appended, some people call all Mendocino processors Celeron-A regardless of clock rate.
The new Mendocino-core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as too successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. Overclockers soon discovered that, given a high-end motherboard, many Celeron 300A CPUs could run reliably at 450 MHz. This was achieved by simply increasing the front-side bus (FSB) clock rate from the stock 66 MHz to the 100 MHz clock of the Pentium II, helped by several facts: the 440BX chipset with nominal support for 100 MHz and correspondent memory had already been on the market, and the internal L2 cache was more tolerant to overclocking than external cache chips, which already had to run at half-CPU speed by design. At this frequency, the budget Mendocino Celeron rivaled the fastest x86 processors available. Some motherboards were designed to prevent this modification, by restricting the Celeron's front side bus to 66 MHz. However, overclockers soon found that putting tape over pin B21 of the Celeron's interface slot circumvented this, allowing a 100 MHz bus.
At the time on-die cache was difficult to manufacture; especially L2 as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock rate as the CPU. All other Intel CPUs at that time used motherboard mounted or slot mounted secondary L2 cache, which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512 KB or 1 MB), but they carried the performance penalty of slower cache performance, typically running at a FSB frequency of 60 to 100 MHz. The Pentium II's 512 KB of L2 cache was implemented with a pair of relatively high-performance L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half the processor's clock rate and communicating with the CPU through a special back-side bus. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked higher and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.
Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533 MHz. The Mendocino Celeron CPU came only designed for a 66 MHz front-side bus, but this would not be a serious performance bottleneck until clock rates reached higher levels.
The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and Socket 370 PPGA package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant; beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed Slotkets) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is they supported symmetric multiprocessing (SMP), and there was at least one motherboard released (the ABIT BP6) which took advantage of this fact.
The Mendocino also came in a mobile variant, with clock rates of 266, 300, 333, 366, 400, 433 and 466 MHz.
In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related Dixon Mobile Pentium II variant.
Coppermine-128
The next generation Celeron was the 'Coppermine-128' (sometimes known as the Celeron II). These were a derivative of Intel's Coppermine Pentium III and were released on March 29, 2000. This Celeron used a Coppermine core with half of its L2 cache switched off, resulting in 128 KB of 4-way associative on-chip L2 cache as on the Mendocino, and was initially likewise restricted to a 66 MHz Front Side Bus speed. Despite the halved associativity on the L2 cache, which reduced hit rates compared to the full Coppermine design, it kept the 256-bit wide L2 cache bus, which meant an advantage compared to Mendocino and older Katmai/Pentium II designs, which all had a 64-bit datapath to their L2 caches. SSE instructions were also enabled.