In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier NMOS (n-type metal-oxide semiconductor) logic families that needed multiple power supply voltages. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many microprocessors and other logic elements.
Depletion-mode n-type MOSFETs as load transistors allow single voltage operation and achieve greater speed than possible with enhancement-load devices alone. This is partly because the depletion-mode MOSFETs can be a better current source approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early PMOS and NMOS chips demanded several voltages).
The inclusion of depletion-mode NMOS transistors in the manufacturing process demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of dopant in the load transistors channel region, in order to adjust their threshold voltage. This is normally performed using ion implantation.
Although the CMOS process replaced most NMOS designs during the 1980s, some depletion-load NMOS designs are still produced, typically in parallel with newer CMOS counterparts. One example of this is the Z84015See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84015. and Z84C15.See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84C15.
History and background
Following the invention of the MOSFET by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959, they demonstrated MOSFET technology in 1960. They fabricated both PMOS and NMOS devices with a 20μm process. However, the NMOS devices were impractical, and only the PMOS type were practical working devices.
In 1965, Chih-Tang Sah, Otto Leistiko and A.S. Grove at Fairchild Semiconductor fabricated several NMOS devices with channel lengths between 8μm and 65μm. Dale L. Critchlow and Robert H. Dennard at IBM also fabricated NMOS devices in the 1960s. The first IBM NMOS product was a memory chip with 1kb data and 50100 ns access time, which entered large-scale manufacturing in the early 1970s. This led to MOS semiconductor memory replacing earlier bipolar and ferrite-core memory technologies in the 1970s.
Silicon gate In the late 1960s, bipolar junction transistors were faster than (p-channel) MOS transistors then used and were more reliable, but they also consumed much more power, required more area, and demanded a more complicated manufacturing process. MOS ICs were considered interesting but inadequate for supplanting the fast bipolar circuits in anything but niche markets, such as low power applications. One of the reasons for the low speed was that MOS transistors had gates made of aluminum which led to considerable parasitic capacitances using the manufacturing processes of the time. The introduction of transistors with gates of polycrystalline silicon (that became the de facto standard from the mid-1970s to early 2000s) was an important first step in order to reduce this handicap. This new self-aligned silicon-gate transistor was introduced by Federico Faggin at Fairchild Semiconductor in early 1968; it was a refinement (and the first working implementation) of ideas and work by John C. Sarace, Tom Klein and Robert W. Bower (around 1966–67) for a transistor with lower parasitic capacitances that could be manufactured as part of an IC (and not only as a discrete component). This new type of pMOS transistor was 3–5 times as fast (per watt) as the aluminum-gate pMOS transistor, and it needed less area, had much lower leakage and higher reliability. The same year, Faggin also built the first IC using the new transistor type, the Fairchild 3708 (8-bit analog multiplexer with decoder), which demonstrated a substantially improved performance over its metal-gate counterpart. In less than 10 years, the silicon gate MOS transistor replaced bipolar circuits as the main vehicle for complex digital ICs.
NMOS and back-gate bias There are a couple of drawbacks associated with PMOS: The electron holes that are the charge (current) carriers in PMOS transistors have lower mobility than the electrons that are the charge carriers in NMOS transistors (a ratio of approximately 2.5), furthermore PMOS circuits do not interface easily with low voltage positive logic such as DTL-logic and TTL-logic (the 7400-series). However, PMOS transistors are relatively easy to make and were therefore developed first — ionic contamination of the gate oxide from etching chemicals and other sources can very easily prevent (the electron based) NMOS transistors from switching off, while the effect in (the electron-hole based) PMOS transistors is much less severe. Fabrication of NMOS transistors therefore has to be many times cleaner than bipolar processing in order to produce working devices.
Early work on NMOS integrated circuit (IC) technology was presented in a brief IBM paper at ISSCC in 1969. Hewlett-Packard then started to develop NMOS IC technology to get the promising speed and easy interfacing for its calculator business.These calculators (like the Datapoint 2200 and others) were in many ways small desktop computers, but preceded the Apple II and the IBM PC by many years. Tom Haswell at HP eventually solved many problems by using purer raw materials (especially aluminum for interconnects) and by adding a bias voltage to make the gate threshold large enough; this back-gate bias remained a de facto standard solution to (mainly) sodium contaminants in the gates until the development of ion implantation (see below). Already by 1970, HP was making good enough nMOS ICs and had characterized it enough so that Dave Maitland was able to write an article about nMOS in the December, 1970 issue of Electronics magazine. However, NMOS remained uncommon in the rest of the semiconductor industry until 1973.Shown by its mere mention in a large roundup article written by GE engineer Herman Schmid that appeared in the December, 1972 issue of IEEE Transactions on Manufacturing Technology. Although it cites Maitland’s 1970 article in Electronics, Schmid’s article does not discuss NMOS fabrication in detail but it does cover PMOS and even CMOS fabrication extensively.
The production-ready NMOS process enabled HP to develop the industry’s first 4-kbit IC ROM. Motorola eventually served as a second source for these products and so became one of the first commercial semiconductor vendors to master the NMOS process, thanks to Hewlett-Packard. A while later, the startup company Intel announced a 1-kbit pMOS DRAM, called 1102, developed as a custom product for Honeywell (an attempt to replace magnetic core memory in their mainframe computers). HP’s calculator engineers, who wanted a similar but more robust product for the 9800 series calculators, contributed IC fabrication experience from their 4-kbit ROM project to help improve Intel DRAM’s reliability, operating-voltage, and temperature range. These efforts contributed to the heavily enhanced Intel 1103 1-kbit pMOS DRAM, which was the world’s first commercially available DRAM IC. It was formally introduced in October 1970, and became Intel’s first really successful product.
Depletion-mode transistors
Early MOS logic had one transistor type, which is enhancement mode so that it can act as a logic switch. Since suitable resistors were hard to make, the logic gates used saturated loads; that is, to make the one type of transistor act as a load resistor, the transistor had to be turned always on by tying its gate to the power supply (the more negative rail for PMOS logic, or the more positive rail for NMOS logic). Since the current in a device connected that way goes as the square of the voltage across the load, it provides poor pullup speed relative to its power consumption when pulled down. A resistor (with the current simply proportional to the voltage) would be better, and a current source (with the current fixed, independent of voltage) better yet. A depletion-mode device with gate tied to the opposite supply rail is a much better load than an enhancement-mode device, acting somewhere between a resistor and a current source.
The first depletion-load NMOS circuits were pioneered and made by the DRAM manufacturer Mostek, which made depletion-mode transistors available for the design of the original Zilog Z80 in 1975–76.Zilog relied on Mostek and Synertek to produce the Z80 and other chips before their own production facilities were ready. Mostek had the ion implantation equipment needed to create a doping profile more precise than possible with diffusion methods, so that the threshold voltage of the load transistors could be adjusted reliably. At Intel, depletion load was introduced in 1974 by Federico Faggin, an ex-Fairchild engineer and later the founder of Zilog. Depletion-load was first employed for a redesign of one of Intel's most important products at the time, a +5V-only 1Kbit NMOS SRAM called the 2102 (using more than 6000 transistorsEach bit demands six transistors in a typical static RAM.). The result of this redesign was the significantly faster 2102A, where the highest performing versions of the chip had access times of less than 100ns, taking MOS memories close to the speed of bipolar RAMs for the first time.See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf
Depletion-load NMOS processes were also used by several other manufacturers to produce many incarnations of popular 8-bit, 16-bit, and 32-bit CPUs. Similarly to early PMOS and NMOS CPU designs using enhancement mode MOSFETs as loads, depletion-load nMOS designs typically employed various types of dynamic logic (rather than just static gates) or pass transistors used as dynamic clocked latches. These techniques can enhance the area-economy considerably although the effect on the speed is complex. Processors built with depletion-load NMOS circuitry include the 6800 (in later versions "Motorola is redesigning the M6800 microprocessor family by adding depletion loads to increase speed and reduce the 6800 CPU size to 160 mils."), the 6502, Signetics 2650, 8085, 6809, 8086, Z8000, NS32016, and many others (whether or not the HMOS processors below are included, as special cases).
A large number of support and peripheral ICs were also implemented using (often static) depletion-load based circuitry. However, there were never any standardized logic families in NMOS, such as the bipolar 7400 series and the CMOS 4000 series, although designs with several second source manufacturers often achieved something of a de facto standard component status. One example of this is the NMOS 8255 PIO design, originally intended as an 8085 peripheral chip, that has been used in Z80 and x86 embedded systems and many other contexts for several decades. Modern low power versions are available as CMOS or BiCMOS implementations, similar to the 7400-series.
Intel HMOS
Intel's own depletion-load NMOS process was known as HMOS, for high density, short channel MOS. The first version was introduced in late 1976 and first used for their static RAM products, it was soon being used for faster and/or less power hungry versions of the 8085, 8086, and other chips.